Method and apparatus for fast lock acquisition in self-biased phase locked loops
US6919769B2 · kind B2 · utility
8Cited by
20References
20Claims
0Family size
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Key dates
| Filing date | Sep 24, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Nov 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/18
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A self-biased phase locked loop (PLL) circuit includes a charge pump to generate a control voltage, a controlled oscillator coupled to the charge pump to generate the output signal based at least in part upon the control voltage, discharge circuitry coupled to the charge pump to discharge the control voltage, and frequency detection circuitry coupled to the controlled oscillator and the discharge circuitry to generate a digital feedback signal for terminating discharge of the control voltage by the discharge circuitry when the output signal reaches a threshold frequency that is a fraction of the target frequency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.