Broadband PIN diode attenuator bias network
US6919774B2 · kind B2 · utility
9Cited by
8References
35Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2001 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jan 25, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H7/255
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Diode network configurations are disclosed in which cathode bias voltage is held substantially constant to provide an attenuator circuit in which return loss is optimized throughout a broad dynamic attenuation range. Preferred embodiments include PIN diodes arranged in a π network having two attenuation control signals provided thereto. Alternative embodiments include PIN diodes arranged in a T network having two attenuation control signals provided thereto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.