CMOS image sensor having row decoder capable of shutter timing control
US6920078B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 12, 2003 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Nov 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A CMOS image sensor having a row decoder capable of shutter timing control is provided, the row decoder addressing to a plurality of pixels arranged in rows and columns in a CMOS image sensor and including a plurality of unit arrays, wherein the unit arrays include a first NAND gate for generating a reset gate signal in response to an address signal and a reset signal, a second NAND gate for generating a selection gate signal in response to the address signal and a selection signal, a latch for resetting an output thereof in response to an address latch signal and latching the address signal as the output in response to the address latch signal and the address signal, a third NAND gate for receiving the address signal and a transmitted signal, a fourth NAND gate for receiving the output of the latch and a shutter transmitted signal, and an OR gate for receiving the outputs of the third and fourth NAND gates and generating a transmitted gate signal; wherein shuttering of a row address is latched in accordance with the blank interval of the horizontal synchronization signal using latches of the row decoder, and the shuttering operation is performed sequentially increasing the shutter…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.