Decision feedback equalizer with embedded coherent signal combiner
US6920333B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Jan 10, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/0349
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver in a communication system, for combining various significant components of a multipath fading signal and eliminating all other small components, consists of a signal generator, a plurality of delay devices, a plurality of decision feedback equalizers with embedded coherent signal combiners, a controller, a coherent signal combiner, and a decision circuit. The first decision feedback equalizer receives its inputs signals from a delay device and a signal generator, and each of the rest decision feedback equalizer receives its input signals from a corresponding delay device and the signal generator of its previous decision feedback equalizer. The coherent signal combiner, coupled to the output of the summation circuit of the last decision feedback equalizer, combines all the significant component signals together. The decision circuit makes a decision on transmitted symbol from the output signal of the coherent signal combiner. The controller collects information from various devices and generates control signals for various devices. Each decision feedback equalizer with embedded coherent signal combiner comprises of a feedforward filter, a feedback filter, a summation circ…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.