Time sharing a single port memory among a plurality of ports
US6920510B2 · kind B2 · utility
9Cited by
13References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 5, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Oct 6, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T9/007
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.