System and method for supporting access to multiple I/O hub nodes in a host bridge
US6920519B1 · kind B1 · utility
42Cited by
28References
32Claims
0Family size
Assignee
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Key dates
| Filing date | May 10, 2000 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | May 10, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/682
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Dynamic routing of data to multiple processor complexes. PCI address space is subdivided among a plurality of processor complexes. Translation table entries at each processor complex determine which processor complex is to receive a DMA transfer, thereby enabling routing of DMA data to one I/O hub node while accessing translation table entries at another I/O hub node. Further, interrupt requests may be dynamically routed to multiple processor complexes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.