Dual-bank FIFO for synchronization of read data in DDR SDRAM
US6920526B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | May 24, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a dual bank FIFO memory buffer operable to buffer read data from memory and thereby compensate for specific timing problems in certain computerized systems. One embodiment of the invention includes a dual bank FIFO that comprises a first bank of memory elements operable to buffer memory data and a second bank of memory elements operable to buffer memory data. Write control address logic is operable to store selected memory data in memory elements with selected addresses within a bank of memory elements, and write control timing logic is operable to selectively grant write access to the banks of memory elements at predetermined time. Also, read control logic operable to read data stored in the first and second banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.