Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor
US6920547B2 · kind B2 · utility
1Cited by
6References
19Claims
0Family size
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Key dates
| Filing date | Dec 20, 2000 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Aug 20, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3863
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Register adjustment is performed based on adjustment values determined at multiple stages within a pipeline of a processor. In one embodiment, a programmable processor is adapted to include a speculative count register. The speculative count register may be loaded with data associated with an instruction before the instruction commits. However, if the instruction is terminated before it commits, the speculative count register may be adjusted. A set of counters may monitor the difference between the speculative count register and its architectural counterpart.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.