Parallel data communication having multiple sync codes
US6920576B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 31, 2001 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Mar 8, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high-speed parallel-data communication approach overcomes skewing problems by transferring digital data with automatic realignment. In one example embodiment, a parallel bus has parallel bus lines adapted to transfer digital data from a data file, along with a synchronizing clock signal. To calibrate the synchronization, the sending module transfers synchronization codes which are sampled and validated according to an edge of the clock signal by a receiving module and then used to time-adjust the edge of the clock signal relative to the synchronization codes. The synchronization codes are implemented to toggle the bus lines with each of the synchronization codes transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.