Method and apparatus for adjusting the phase of an output of a phase-locked loop
US6920622B1 · kind B1 · utility
19Cited by
20References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 2, 2002 |
| Grant date | Jul 19, 2005 |
| Priority date | — |
| Expiry date | Aug 1, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/197
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit receives a request to adjust the phase of an output clock being generated by a phase-locked loop based on an input reference clock. A digital or analog offset value is injected into the phase-locked loop based on a phase adjustment amount contained in the phase adjustment request. Alternatively, a programmable delay is implemented in the PLL feedback path or the reference clock path. The delay is based on the phase adjustment request.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.