Wafer-scale manufacturing method
US6921676B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Sep 12, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The wafer-scale assembly method provides first elements arrayed on a wafer with adjacent ones of the first elements separated by a predetermined spacing. Second elements are also provided. A spacing-defining jig is provided that includes recesses corresponding in size to the second elements. Adjacent ones of the recesses are separated by a spacing equal to the predetermined spacing. The second elements are inserted into the recesses of the spacing-defining jig and are then affixed to the wafer with the second elements in alignment with corresponding ones of the first elements. Inserting the second elements in to the jig in which the recesses are separated by a spacing equal to the predetermined spacing allows a single alignment operation to provide accurate alignment between all the first elements, e.g., image sensors, arrayed on the wafer and all the second elements, e.g., lens assemblies, that are to be affixed to the first elements arrayed on the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.