Structure of a lateral diffusion MOS transistor in widespread use as a power control device
US6921942B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 2004 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Jan 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a semiconductor device structured so as to be mounted jointly with other devices on one chip, and capable of controlling a large current in spite of a small device area while having small on-resistance, thereby enabling a high voltage resistance to be obtained. In the case of NLDMOS, the semiconductor device comprises an N well layer, formed on a p-type semiconductor substrate, a P well layer formed in the N well layer, a source electrode formed in a source trench cavity within the P well layer, a gate electrode formed in at least one of gate trench cavities within the P well layer, through the intermediary of an oxide film, and a drain electrode formed in a drain trench cavity within the N well layer, and further, N+ diffused layers are formed, around the source trench cavity, the drain trench cavity, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.