Multiple synthesized clocks with fractional PPM control from a single clock source
US6922109B2 · kind B2 · utility
5Cited by
7References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2002 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Nov 4, 2022 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.