Apparatus and method for recalibrating a source-synchronous pipelined self-timed bus interface
US6922789B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2001 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Apr 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0008
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.