System and method for achieving timing closure in fixed placed designs after implementing logic changes
US6922817B2 · kind B2 · utility
25Cited by
13References
18Claims
0Family size
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Key dates
| Filing date | Apr 4, 2003 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Sep 10, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for implementing logic changes in integrated circuits (ICs). In a preferred embodiment, donor logic elements are taken from donator logic paths. The donated cells are implemented into a logic path altered by an ECO. The donated cell is replaced by spare cells. Timing analysis is done to ensure all logic paths are timing closed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.