Method for creating derivative integrated circuit layouts for related products
US6922823B2 · kind B2 · utility
13Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 13, 2002 |
| Grant date | Jul 26, 2005 |
| Priority date | — |
| Expiry date | Feb 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for creating a derivative semiconductor design layout is disclosed. The method generally comprises the steps of (A) receiving a plurality of changes from a user for a first layout of a semiconductor design having a plurality of first layers, (B) storing the changes in a plurality of second layers and (C) displaying the derivative semiconductor design layout to the user in response to logically operating on the first layers and the second layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.