Patent · US Expired

Stacked memory device having shared bitlines and method of making the same

US6925015B2 · kind B2 · utility

3Cited by

12References

20Claims

0Family size

Assignee

Intel Corporation · US

Inventors

John I. Garney · Beaverton, US
David Chow · West Chester, US
Rick Coulson · Portland, US

Key dates

Filing date	Nov 26, 2002
Grant date	Aug 2, 2005
Priority date	—
Expiry date	Mar 16, 2023

Classification

Technology area (CPC G)Physics
CPC primaryG11C7/18
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Briefly, in accordance with one embodiment of the invention, a system includes a memory array. The memory array comprises a first layer of memory cells overlying a second layer of memory cells and bit lined coupled to at least one memory cell in the first layer of memory cells and to at least one memory cell in the second layer of memory cell.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.