Digital-data receiver synchronization
US6925135B2 · kind B2 · utility
18Cited by
23References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 25, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0685
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Digital-data receiver synchronization is provided with composite phase-frequency detectors, mutually cross-connected comparison feedback or both to provide robust reception of digital data signals. A single master clock can be used to provide frequency signals. Advantages can include fast lock-up time in moderately to severely noisy conditions, greater tolerance to noise and jitter when locked, and improved tolerance to clock asymmetries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.