Method, apparatus and computer program product for efficient per thread performance information
US6925424B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 16, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Jan 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, remains consistent despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent way to update performance counts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.