Packet buffer memory with integrated allocation/de-allocation circuit
US6925544B2 · kind B2 · utility
6Cited by
3References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 9, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Dec 26, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A buffer memory with a memory allocation and de-allocation circuit. The buffer memory has an address space divided into address blocks and a memory address space divided into memory blocks. The circuit, in response to an allocation request for an allocation of a certain size buffer, allocates sufficient address blocks and memory blocks for the buffer. The circuit, in response to a de-allocation request to de-allocate a certain size of memory, de-allocates whole unused address blocks and memory blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.