Systems and methods for testing processors
US6925584B2 · kind B2 · utility
9Cited by
20References
36Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 30, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Apr 30, 2023 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB23K2101/40
- WIPO fieldMachine tools
- WIPO sectorMechanical engineering
Abstract
Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.