Method of routing a redistribution layer trace in an integrated circuit die
US6925626B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2003 |
| Grant date | Aug 2, 2005 |
| Priority date | — |
| Expiry date | Dec 25, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of routing a metal layer trace in an integrated circuit die includes steps of: (a) receiving as input a netlist of an integrated circuit die; (b) selecting a redistribution layer trace from the netlist for routing the redistribution layer trace between an I/O pad of the integrated circuit die and a termination point; (c) comparing a trace width of the redistribution layer trace with a maximum trace width limit; and (d) if the trace width of the redistribution layer trace exceeds the maximum trace width limit, then routing the redistribution layer trace as a plurality of separate parallel traces each having a trace width that is less than the selected maximum trace width limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.