Semidigital delay-locked loop using an analog-based finite state machine
US6927611B2 · kind B2 · utility
27Cited by
2References
16Claims
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Key dates
| Filing date | Oct 29, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Oct 29, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a controllable delay element, such as, a phase rotator, for data edge tracking.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.