Method and system for reducing leakage current in integrated circuits using adaptively adjusted source voltages
US6927619B1 · kind B1 · utility
23Cited by
5References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 6, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | May 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0013
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus for reducing leakage currents in an integrated circuit having logic gates containing PMOS devices and NMOS devices. The apparatus comprises a power management unit capable of: i) applying a fixed VDD supply voltage to body connections of said PMOS devices; ii) applying a fixed VSS supply voltage to body connections of said NMOS devices; iii) applying an adjustable PMOS source voltage to sources of said PMOS devices; and iv) applying an adjustable NMOS source voltage to sources of said NMOS devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.