PLL with multiple tuning loops
US6927638B2 · kind B2 · utility
4Cited by
1References
14Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 29, 2003 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Jan 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Some embodiments provide a charge pump to output a first control signal and a second control signal based on a frequency of an oscillating signal and a reference frequency, a switch capacitor circuit to generate a first output capacitance based on the first control signal, a main loop circuit to generate an output signal based on the second control signal, and an oscillating circuit to generate the oscillating signal, the frequency of the oscillating signal based at least on the first output capacitance and the output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.