Duty cycle correction method for frequency synthesis
US6927642B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2004 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Mar 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction method converts a pair of differential analog signals from an oscillator into an output pulse signal with 50% of duty cycle. The pulse signal has the same frequency as that of each of the differential analog signals. The duty cycle correction method processes the pair of differential analog signals into a first digital pulse signal and a second digital pulse signal, wherein the first digital pulse signal and the second digital pulse signal have a specified phase difference therebetween, frequency-divides the first digital pulse signal and the second digital pulse signal into a third digital pulse signal and a fourth digital pulse signal, and generates the output pulse signal according to the third and fourth digital pulse signals. The output pulse signal can be generated by performing an exclusive OR operation of the third and fourth digital pulse signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.