Patent · US Expired

Variable modulus interpolator, and a variable frequency synthesizer incorporating the variable modulus interpolator

US6927716B2 · kind B2 · utility

17Cited by
12References
41Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJun 14, 2002
Grant dateAug 9, 2005
Priority date
Expiry dateFeb 19, 2023

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH03L7/1976
  • WIPO fieldBasic communication processes
  • WIPO sectorElectrical engineering

Abstract

A variable modulus interpolator (1) for interpolating a fractional part of a rational number by which a reference frequency is to be divided in a multi-divisor divider in a variable frequency synthesizer comprises a third order sigma-delta modulator (3) of MASH cascade configuration having first, second and third sigma-delta stages (5,6,7). The numerator F of the fraction is selectable and is inputted to a first register (10) for inputting to the input of the first sigma-delta stage (5) of the sigma-delta modulator (3). The denominator M of the fraction is selectable and is inputted to a second register 11. A single bit output quantiser (16) in each sigma-delta stage (5,6,7) outputs a sign bit indicative of the sign of the output from an integrator (15) in the corresponding sigma-delta stage (5,6,7). A multiplier (22) is located in the negative feedback loop of each sigma-delta modulator for multiplying the output of the quantiser (16) being fed back by the denominator M stored in the second register (11). The negative of the fed back product of the multiplier and the quantiser output is summed in a first summer (18) in the corresponding sigma-delta stage (5,6,7) with the input to …

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.