Method and device for sequential readout of a memory with address jump
US6928530B2 · kind B2 · utility
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2References
23Claims
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Key dates
| Filing date | Feb 22, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Jun 12, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.