Fault tolerant scan chain for a parallel processing system
US6928606B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2002 |
| Grant date | Aug 9, 2005 |
| Priority date | — |
| Expiry date | Jan 27, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318536
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A highly robust fault tolerant scan chain is designed for scanning (and/or controlling a configuration of) a parallel processing system. The scan chain implements parallel redundant scan chains that follow physically diverse paths through the parallel processing system. For each IC under test, a set of redundant TAPs perform a boundary scan, and the test results are combined by voting. The TAPs of each set are physically diverse, in that they are physically located in separate power domains of the parallel processing system. As a result, the scan chain is robust to faults affecting power and/or control signal supply to any one power domain. Respective input and output dummy cells at opposite extreme ends of the scan chain provide a graceful separation and recombination of the redundant parallel scan chains, and so renders the architecture of the scan chain transparent to external boundary scan circuit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.