METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT, INTEGRATED CIRCUIT OBTAINED IN ACCORDANCE WITH SAID METHOD, WAFER PROVIDED WITH AN INTEGRATED CIRCUIT OBTAINED IN ACCORDANCE WITH THE METHOD, AND SYSTEM COMPRISING AN INTEGRATED CIRCUIT OBTAINED BY MEANS OF THE METHOD
US6930499B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jan 31, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The invention relates to a method of manufacturing an integrated circuit (404) on a die (402), wherein the die (402) forms a detachable part of a wafer (401) comprising a plurality of dies that are separated from each other by dicing lanes (403). The method comprises a step of applying a metallization pattern (407) in at least one of the dicing lanes (403) to form a communication bus comprising at least one communication bus circuit (405) that is part of the integrated circuit (404). Said step is followed by a step wherein the integrated circuit (404) is tested according to a predetermined testing method which uses the communication bus circuit (405) to communicate with the integrated circuit (404). This step is followed by a next step wherein the die (402) is detached from the wafer (401). The communication bus circuit (405) is designed so as to communicate in a wafer test mode as well as in a functional mode. During the testing of the integrated circuit (404), it communicates in the wafer test mode. The invention also relates to an integrated circuit (404) obtained by means of the manufacturing method, a wafer (401) comprising an integrated circuit (404) obtained by means of the …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.