Self-biasing differential buffer with transmission-gate bias generator
US6930550B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 26, 2004 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 26, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0272
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A self-biasing differential buffer generates a self-bias voltage from its inputs. A first amplifier receives a first input signal on gates of four transistors—p and n-channel drive transistors in a drive branch and p and n-channel bias-generating transistors in a bias-generating branch. Current source and current sink transistors source and sink current to both branches. The drains of the drive transistors drive a differential output, while the drains of the bias-generating transistors drive through a transmission gate to a self-bias node. The second amplifier receives the second input signal and has the same structure, with one branch driving the self-bias voltage through another transmission gate, and another branch driving a complementary differential output. The bias-generating branches use smaller transistors so that only a small current is used to generate the self-bias voltage. The self-bias node is fed to the gates of current source and sink transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.