Zero voltage class AB minimal delay output stage and method
US6930551B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2003 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Aug 28, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/30015
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A class AB output circuit includes a P-channel pullup transistor (M13) having a source coupled to a supply voltage, a drain coupled to an output(10), a gate coupled to respond to an input signal on an input(9), an N-channel pulldown transistor (M1) having a drain coupled to the output, a source coupled to ground, and a gate coupled to respond to the input signal. A first N-channel transistor (M2) has a drain coupled to a gate of the output transistor and the supply voltage by means of a current source (8) and a source coupled to ground by means of a second current source (13). A first diode-connected N-channel transistor (M3), a second diode-connected N-channel transistor (M4), and a first level shifting circuit (17) are coupled in series between ground and a gate of the N-channel transistor, and a current source (7) is coupled between the first supply voltage and the gate of the first N-channel transistor. A second level shifting circuit (18) is coupled between the gate of the pulldown transistor and the source of the first N-channel transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.