Shared memory architecture in GPS signal processing
US6930634B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Mar 28, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S19/37
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.