Simultaneous read-write memory cell at the bit level for a graphics display
US6930929B1 · kind B1 · utility
1Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 4, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Sep 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved memory for graphics displays includes an improved memory cell. Data may be written and read from the single bit cell simultaneously, eliminating the need for additional memory circuits to service an N column driver for a display. Additionally, the architecture of the memory allows for a signal input port for writing the data to the cell while allowing for multiple parallel output ports for reading the data. The unique architecture eliminates the need for addressing logic and refresh circuitry for display applications.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.