Redundancy circuit and semiconductor device using the same
US6930935B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2004 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Feb 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/785
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy control circuit includes a redundancy decoder and a decoder killer circuit. The redundancy decoder includes a plurality of fuse circuits corresponding to a plurality of determination signals which are previously activated, and each of the plurality of fuse circuits contains a plurality of fuse sections each containing a fuse. The decoder killer circuit generates a killer signal when at least one of the plurality of determination signals is active, and the killer signal is outputted to an external unit in a first check mode. One of the plurality of fuse circuits is selected and determination signals corresponding to non-selected fuse circuits are inactivated. A specific fuse section of the selected fuse circuit inactivates the determination signal to provide indication of whether the fuse section is cut.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.