Digital phase locked loop
US6931082B2 · kind B2 · utility
0Cited by
9References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2001 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jul 18, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D3/241
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A technique that enables the sine and cosine branches within a PLL module to be obtained relatively easily and efficiently is described. According to the technique, the computation operations requiring a computation load, such as calculation of sine and cosine functions, are performed mostly once per a digital sampled signal, while relatively simple operations, such as multiplication and accumulations, are performed for every frame.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.