Soft mute circuit
US6931124B1 · kind B1 · utility
4Cited by
25References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2000 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jan 13, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M1/6016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A soft mute circuit includes a programmable amplifier controlled by a register. Data is stored in the register from an adder that combines the current data in the register with a second number for increasing or decreasing the gain of the amplifier. A summation circuit includes a plurality of inputs coupled by gates to a summation node and the summation node is coupled to an input of the programmable amplifier. The gates are controlled by suitable logic for selecting input signals in any combination. A control loop maintains the gain of the amplifier at a predetermined level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.