Method, apparatus and computer program product for efficient, large counts of per thread performance events
US6931354B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2003 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Jan 13, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/88
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Performance events are counted for a computing system. This includes designating a first processor counter as a low-order counter for counting a certain performance event encountered by the processor and associating with the first counter a second counter as a high-order counter. The first counter is incremented responsive to detecting the performance event for a first processing thread. Responsive to a second thread, an accumulator in system memory for the first thread and first and second counters is updated. Responsive to the first thread becoming active, values of the first and second counters are loaded from the accumulator. Responsive to a user call to read and return a combined value, a first instance of the second counter is read, then the first counter is read and a second instance of the second counter is read before returning the combined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.