Reprogrammable input-output pins for forming different chip or board interfaces
US6931466B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 28, 2001 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Feb 26, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a reprogrammable I/O system for a chip or board system that can be reprogrammed to simulate many I/O interfaces in firmware. The reprogrammable I/O system comprises an I/O cluster, an I/O bus, I/O pins, and logic at the I/O pins. The I/O pins are arranged logically in a row and are grouped into pin groups of eight pins. Each pin group also includes a pin state machine (PSM) and a data FIFO coupled together. Each PSM has chain connections to the two neighboring PSM's. Each data FIFO has chain connections to the two neighbor data FIFO's. The reprogrammable I/O system allows firmware to organize the I/O pins into I/O interfaces. The firmware in PSM's and the I/O cluster that control the operations of the I/O pins can be changed (reprogrammed) so that the I/O system can perform other different interfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.