High performance multi-controller processing
US6931487B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 22, 2001 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Oct 17, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/85
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for high performance multi-controller processing is disclosed. Independent Network storage controllers (NSCs) are connected by a high-speed data link. The NSCs control a plurality of storage devices connected by a Fiber Channel Arbitrated Loop (FCAL). To provide redundancy, for a given logical unit of storage one NSC will function as the primary controller and the other NSC will function as a mirror controller. To enhance the efficiency of command-response data transfers between NSCs, mirror memory is correlated with primary memory and named resources are used for command-response data transfers. Methods are disclosed to provide for efficient active mirroring of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.