Fail-over control in a computer system having redundant service processors
US6931568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2002 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Oct 1, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2038
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for determining an active service processor from two or more redundant service processors in the system. The system typically includes two management modules and at least one managed subsystem such as a server blade. Each management module includes a service processor and control logic. The control logic is configured to receive various status signals from the service processor and to generate a control signal based thereon. The control signal is provided, via an interconnect plane, to determination logic on each managed subsystem. The determination logic receives a control signal from each management module and generates a switch signal based on the state of the control signals. The switch signal controls switching logic configured to receive bus signals from the service processors on each management module. Based on the control signal, one of the service processor bus signals is provided to managed instrumentation on the managed subsystem. The management module control logic is generally configured to maintain the control signal in its current state if the active processor is determined to be functional. The control logic is further configured to alter the con…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.