Method and apparatus for handling transient memory errors
US6931571B2 · kind B2 · utility
7Cited by
9References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2001 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 23, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0751
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for managing memory of a data processing system. In one embodiment, memory objects are allocated in response to memory allocation requests. Each object has an associated plurality of addresses. Type-identifier codes are respectively stored in association with the memory objects. Upon detection of a transient memory error at a memory address a recovery action is selected and performed based on the type-identifier code of the object that is associated with the erring memory address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.