Method for rapid estimation of wire delays and capacitances based on placement of cells
US6931610B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2000 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fast method of estimating capacitances and wire delays in an integrated circuit design is based on placement information such as that contained in a gate schematic net list from a logic synthesis tool. A simple tree topology called a spine tree is constructed to connect the pins of the net as an approximation of actual connections therein. Capacitance is extracted for this topology assuming a worst case scenario, and Elmore delays are computed for the wire delays based on the worst-case capacitances. The method takes linear time as a function of the number of pins in the net and is much faster than using a Steiner tree method in this context.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.