Controller for multiple instruction thread processors
US6931641B1 · kind B1 · utility
69Cited by
17References
11Claims
0Family size
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Key dates
| Filing date | Apr 4, 2000 |
| Grant date | Aug 16, 2005 |
| Priority date | — |
| Expiry date | Apr 4, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3851
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism controls a multi-thread processor so that when a fist thread encounters a latency event to a first predefined time interval temporary control is transferred to an alternate execution thread for duration of the first predefined time interval and then back to the original thread. The mechanism grants full control to the alternate execution thread when a latency event for a second predefined time interval is encountered. The first predefined time interval is termed short latency event whereas the second time interval is termed long latency event.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.