Insulated multilayered substrate having connecting leads for mounting a semiconductor element thereon
US6931724B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2002 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jul 30, 2022 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49345
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of producing a multilayered substrate having: a first face being provided with pads bondable to electrode terminals of a semiconductor element, and a body containing a plurality of wiring line layers and insulation layers successively formed from the side of the multilayered substrate at which the face for mounting a semiconductor element is located, wherein the final insulating layer forms provides a second face of the multilayered substrate. The successive wiring line layers are connected by vias, and the second face has external connection terminal pads. The pads on the first face are formed on a metal sheet, a first layer of insulating material is formed on the metal sheet so as to cover the pads formed thereon, holes are formed through the insulating material to expose the end face of the pad, and a patterned metal layer is formed to provide a layer of wiring lines and vias connecting the pads with the wiring line on the layer of insulating material. Subsequently, layers of insulation material are formed to cover the layers of wiring lines, where vias are formed in the insulating material layers, and then patterned metal wiring line layers and filled vias are formed, …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.