Selective solder bump application
US6933611B2 · kind B2 · utility
1Cited by
1References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Sep 15, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Selective application of solder bumps in an integrated circuit package. Solder bumps are selectively applied in a solder bump integrated circuit packaging process so that portions of a circuit can be effectively disabled. The bumps may be selectively applied either to a die or to the substrate using multiple solder masks, one for each pattern of solder bumps desired or can be otherwise applied in multiple patterns depending upon which portions of the circuitry are to be active and which are to be disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.