Dual mode analog differential and CMOS logic circuit
US6933743B2 · kind B2 · utility
4Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Nov 20, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Jan 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31701
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A dual mode, analog differential and complementary metal oxide semiconductor (CMOS) logic circuit is provided. The circuit includes a differential input for receiving a differential input signal. A switch pair is coupled to the differential input. A pair of load resistors coupled to the switch pair defines a differential output for providing a differential output signal. A current source is coupled to the switch pair. A control input receives a control signal and control circuitry coupled to the control input disable the current source to select a CMOS testing mode responsive to the control signal being activated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.