Systems and methods of performing duty cycle control
US6933759B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 5, 2004 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Feb 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention facilitates serial communication by performing duty cycle correction. A duty cycle correction component 302 performs duty cycle corrections on a pair of differential sinusoidal signals according to a pair of adjustment signals and, as a result, generates a differential pair of square wave signals. A cross coupled buffer 306 buffers the differential pair of square wave signals and provides the buffered signals to a feedback circuit 304 that measures duty cycles of the signals and generates the pair of adjustment signals accordingly. The buffer 306 can also remove skew from the signals. In a transmitter 102, the buffered signals are also generally provided to a multiplexer 112 or encoder and in a receiver 106, the buffered signals are also generally provided to a sampling component 122.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.