Variable data rate receiver
US6933866B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 14, 2004 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Sep 14, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M5/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock signal and data is recovered from a variable rate signal including biphase mark encoded digital audio data. Such recovery involves regularly determining a minimum or maximum pulse width in the biphase mark encoded digital audio data using a high frequency clock. This pulse width is used to define a window in which a transition in the biphase mark encoded digital audio data may be detected. If a transition occurs in the defined window, a data one is output; if a transition does not occur in the defined window, a data zero is output. The recovered clock has a period of twice the minimum pulse width. A minimum or maximum pulse width can be tracked with an accumulator with decay. In particular, if the data rate of the input signal becomes faster, the shortest pulse will become shorter and a minimum value stored by the accumulator will become shorter. If the data rate of the input signal becomes slower, the longest pulse will become longer and any maximum value stored by the accumulator will become longer. However, if a minimum is stored and the input signal becomes slower, or if a maximum is stored and the input signal becomes faster, the stored minimum or maximum values would …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.