Design for a non-blocking cache for texture mapping
US6933945B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 31, 2003 |
| Grant date | Aug 23, 2005 |
| Priority date | — |
| Expiry date | Nov 9, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0875
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A non-blocking cache for texture mapping is implemented by separating Cache Tags from Cache Data. Multiple requests for data may be processed in parallel without strict ordering or synchronization. Separating Cache Tags and Cache Data results in a texture memory cache design that preempts stalling which would otherwise occur in case of cache-misses. Multiple Cache Tags with corresponding respective system memory controllers and Data Cache units allow for simultaneous processing of multiple requests without strict ordering. In preferred embodiments the texture memory cache may also be configured to predict cache misses and merge with burst reads from memory, and may equally be configured to minimize memory read-requests necessary during multitexturing, thus maximizing bandwidth.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.